1. Field of the Invention
The present invention relates to a semiconductor device in which a field effect semiconductor element is formed in a resin mold package and a method of making the same.
2. Description of the Background Art
FIG. 6(a) is a perspective view schematically showing the appearance of a conventional resin mold field effect semiconductor device SD.sub.p (simply referred to as a "semiconductor device" hereinafter). FIG. 6(b) is a perspective view schematically showing the internal structure of the semiconductor device SD.sub.p of FIG. 6(a).
The semiconductor device SD.sub.p includes a semiconductor element 10, in which a power MOS field effect transistor (hereinafter referred to as a "power MOSFET") whose major face is the (111) plane of silicon single crystal is formed. The semiconductor element 10 (a power MOSFET chip) is fixed to the surface of a metal plate 3 made of Cu and the like with a brazing filler metal 2.
An extraction electrode layer not shown is provided on the top face of the semiconductor element 10, and is connected to external terminals 5 through inner lead wires 4 joined therewith by wire bonding. There is formed a passivation film 6 such as varnish on the surface of the semiconductor element 10. After the structure shown in FIG. 6(b) is formed, the semiconductor element 10 and the metal plate 3 are sealed in a resin 70 such as an epoxy resin by means of a transfer molding technology. Finally formed is the semiconductor device SD.sub.p in the shape shown in FIG. 6(a).
In the conventional semiconductor device SD.sub.p, the resin 70 having a linear expansion coefficient approximate to that of the semiconductor element 10 is selectively used. For instance, such a resin is obtained by adding appropriate filler material to the epoxy resin and the like. The purpose of this addition is to relax the thermal stress generated in the interface between the resin 70 and the semiconductor element 1 resulting from change in an environmental temperature in using the semiconductor device SD.sub.p or from temperature rise by the exothermic reaction of the semiconductor element 10 itself. This enables the prevention of the generation of cracks and chip fractures in the semiconductor element 10.
For a large current flow in the semiconductor device SD.sub.p of the present invention in which the semiconductor element 10 is used as the power MOSFET, it is preferable that a drain-source ON resistance R.sub.on (simply referred to as an "ON resistance" hereinafter) is as small as possible. However, the ON resistance R.sub.on is relatively large (about 1 106 at 25.degree. C.) in the conventional structure mentioned above.
Thus the achievement of a semiconductor device has been desired, in which the ON resistance R.sub.on is smaller than the conventional one while relaxing the thermal stress applied to the semiconductor element 10 to prevent the chip cracks.